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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
FSK Modulation
the HMc700LP4(E) is capable of a simple binary Frequency Shift Keying (FSK) modulation. the internal modulation
is unshaped FSK. the loop bandwidth of the synthesizer must be fixed by the user to achieve symbol shaping as
required.
When the FSK mode of operation is enabled, via fsk_enable (table 13), and SEn is held low, the synthesizer will
output binary FSK frequency hops in response to data input on the SDi pin. When SEn is set, the FSK modulation will
stop and return to f0. ScK must not be toggled when transmitting data in FSK mode.
FSK modulation is normally defined by a deviation, Δ, and a modulation rate, m. the deviation is defined as the
difference between the frequency transmitted when input data is 0, 0, and the frequency transmitted when the input
data is 1, 1.
o
is the frequency programmed in the frequency registers as was defined in (EQ 4),
that is:
1
is the fractional frequency achieved by adding the value in the seed register to the
value in the frac register, that is:
Where
Nint
is the integer division ratio, an integer number between 36 and 65,567 (see integer
register)
Nfrac
is the fractional part, a number from 1 to 224
Nseed
is the seed part, a number from 1 to 224
R
is the reference path division ratio
ref
is the frequency of the external reference input
in this case the deviation Δf is given simply by
FSK data bits on SDi will be latched into the synthesizer on the falling edge of the divided reference rate, PFD. if for
example r=1, and ref = 50 MHz, the input FSK data would be oversampled every 20nsec on the falling edge of the
input reference.
the m rate of the FSK data is simply the inverse of twice the period of the data bits. For example, if the data bit period
is 1msec the fm rate is 500 Hz.
if an unshaped binary FSK is desired, the closed loop bandwidth of the synthesizer should be larger than the m
rate by a sufficient margin. For practical FSK transmissions the m rate is limited by the radio link budget, channel
spectral emission restrictions and practical closed loop bandwidths of the fractional synthesizer.
(EQ 7)
(EQ 8)
(EQ 9)
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相关代理商/技术参数
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HMC703LP4E 功能描述:IC FRACT-N PLL W/SWEEPR 24QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP(0.175",4.40mm 宽) 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR